The present invention relates to operations verifications in electronic devices powered by a varying power source and, more particularly, to a system and method of automatic isolation of battery backed DRAM controller inputs from processor outputs upon power shutdown.
Many electronic devices are powered by a varying or fluctuating power source. A common power source for electronics devices is a battery. Power supplied by a battery varies because of depletion over time of the battery's charge. Other power sources for electronics devices may also vary, either by depletion or in other manners.
Electronics devices, for desired operations of those devices, often require power supplies that are maintained within certain minimum or maximum limits. This may be true, for example, for electronics devices incorporating certain processing capabilities. As power wanes or reaches critical limits, processor operations may vary from normal, expected operations. Some of the reasons for that variation in operations caused by power supply variations may include, for example, clock rate, signal timing, inappropriate interrupt generation, and a wide variety of others.
Certain types of electronics devices, in particular, digital devices, may require or include some type of memory storage. There are various types of memories that are known. Those memories may be employed in electronics devices, for example, in conjunction with a processor. A particular type of memory, known as dynamic random access memory (DRAM), is a read/write type of semiconductor memory that uses a capacitor as the storage cell. DRAMs must be repeatedly refreshed or their data will be lost. In order to accomplish the repeated refreshment and also to allocate information to DRAM storage locations, a DRAM controller is typically employed in conjunction with the DRAM to manage those functions.
A special type of processor for electronics devices is a digital signal processor (DSP). DSPs may be employed in a wide variety of applications. In many of those applications, it is desirable to use some form of memory in conjunction with the DSP, for example, for storage of DSP outputs. DRAM, for example, may serve as memory in conjunction with DSP operations.
DSPs, like various other processors, may perform irregularly when a power supply to the DSP varies. A DSP powered by a battery, for example, may output floating (high-impedance) state signals when power to the DSP is lost or substantially reduced. This may occur upon a total loss of power or, as is common, when a battery power source is depleted to a minimum, critical level of power. In that instance of power source depletion, memory serving for DSP output storage may receive the DSPs floating state output signals and, thus, the memory may contain corrupt data. This may be the case, for example, when the memory is DRAM. As previously mentioned, DRAM is dynamic memory and must be repeatedly refreshed and so is typically controlled by a DRAM controller. If faulty output signals from a DSP are input to a DRAM controller, the data stored in the DRAM controlled by the controller will be corrupted.
The present invention overcomes the problems associated with power variation, such as, for example, critically low battery power previously described. In particular, embodiments of the invention may serve to prevent corruption of DRAM and data therein stored because of faulty DSP output signals input to a DRAM controller, attributable to lost or depleted battery supply. The present invention, thus, provides significant advantages and improvements in the art and technology.